1. Field of the Invention
This invention relates to a multiplication circuit used in a digital operational processor and, particularly, to a multiplication circuit for implementing at a high speed the multiplication process for the fractional part in floating point operations.
2. Description of the Prior Art
A conventional high-speed multiplication circuit, as proposed in Japanese Patent Unexamined Publication No. 58-101343 for example, comprises means for dividing or slicing a multiplier, a decoder for decoding the resulting sliced multipliers, a multiplying unit made of a multiple-gate for multiplying the decoded multipliers with a multiplicand, a carry-save-adder (CSA) which is a multi-input adder for summing sequentially the results of multiplication for the sliced multipliers and the multiplicand, and a carry-propagating adder (CPA) for adding the carry component to the sum component produced by the CSA to produce a final multiplication result. The multiplier slicing method is a known technique as has been introduced in Chapter 5 of "Computer Arithmetic PRINCIPLES, ARCHITECTURE AND DESIGN" by Kai Hwang published in 1979 by John Wiley & Sons Inc. The multiplying operation by the above-mentioned multiplication circuit takes place in such a way that the multiple-gate multiplies the lowest-order multiplier decoded by the decoder with a multiplicand to produce a partial product, the CSA implements summation to produce a partial sum and partial carry, the multiple-gate multiplies the next higher-order multiplier with the multiplicand to produce a partial product, the CSA sums the partial product and the previously obtained partial sum and partial carry which are shifted by a certain number of bits for place adjustment so as to produce a partial sum and partial carry, and the process for producing a new partial sum and partial carry is repeated, each time a partial product is produced, by summing the partial product and a previous partial sum and partial carry while shifting them by a certain number of bits. The conventional multiplication technique necessitates the bit shift operation for each of the partial sum and partial carry, which results disadvantageously in an increased number of terminals used for the shift operation when the multiplying unit is constructed using a plurality of LSI devices.